1. Field of the Invention
The present invention relates generally to methods for semiconductor fabrication, and more particularly to a method for planarizing interlevel dielectric layers.
Planarization of interlevel dielectric layers in multi-level systems is necessary to lessen or eliminate abrupt topographical variations which would otherwise result in metallization discontinuities or unsatisfactory lithographic pattern transfer. One common approach for planarizing dielectric layers is referred to as the "etch back" technique, where a sacrificial layer, usually an organic photoresist, is spin-coated on a wafer after the dielectric film has been formed on top of an uneven surface, such as a patterned metallization layer or polysilicon features formed over the substrate. The dielectric layer generally conforms to the underlying surface profile so that the dielectric displays an uneven upper surface.
Planarization is then carried out by etching back the combined sacrificial and dielectric layers in a manner which substantially retains the planarity defined by the sacrificial layer. Usually, a plasma etchant is selected which is capable of etching both the sacrificial layer material and the dielectric layer material at approximately the same rate.
The present invention is concerned primarily with a method for detecting when the dielectric layer has been etched back by a preselected amount, either fully so that the underlying features are exposed or partially so that the underlying feature remains covered by a desired thickness of the dielectric material. Full exposure will be necessary, for example, in pillar technologies where an overlying metallization layer is connected to source, drain, and polycrystalline silicon lines or to underlying metallization layers by vertical metal columns, referred to as pillars. Usually, the substrate includes the metal pillars or lines, polycrystalline silicon regions, and field oxide regions which together define a very irregular surface. The dielectric layer conforms closely to the substrate, and coverage by the sacrificial layer produces a film of varying thickness which is usually thin over small or narrow features, but thick over broad features or over densely-packed small features. Pillar technology requires that the intermetallic dielectric must be removed from the top of all pillars in order to make contact with an overlying metallization layer. Sufficient dielectric thickness, however, should be maintained over other portions of the substrate after etch back planarization so that these portions remain electrically isolated.
Partial etch back planarization of the dielectric layer will be desirable when interlevel connections are to be formed using via technology. For example, when an interlevel dielectric layer is formed by Chemical Vapor Deposition over the substrate, it generally conforms to the underlying uneven topography, interfering with subsequent process steps, such as patterning and etching of overlying vias and metallization layers. It is therefore desirable that the interlevel dielectric be at least partially smoothed prior to via formation. The desired smoothing can be achieved by etch back planarization to an intermediate level within the dielectric layer, as is well known.
A problem which is encountered in both full and partial etch back planarization is the lack of an etch stop barrier to provide for termination of the etch. Without such a barrier, it is difficult to determine the appropriate point at which to stop etching. Heretofore, etching has been stopped after a preselected time period based on the expected etch rate under the particular etch conditions. Although generally workable, reliance on timing alone can cause either over-etching or under-etching, neither of which is satisfactory.
It is therefore desirable to provide improved planarization methods useful for smoothing interlevel and intermetallic dielectric layers. In pillar technology, such methods should provide for positive confirmation of the exposure of underlying metallization regions, particularly broad regions of metallization which are covered by relatively thick planarization layers. Similarly, they should provide for a clear indication when a desired partial etch back is achieved in via technology.
2. Description of the Background Art
Adams and Capio (1981) J. Electrochem. Soc. 128:423 describe conventional etch back techniques useful for dielectric planarization. Spectroscopic determination of end points in non-planarization etch processes is described in Marcoux et al. (1981) Solid State Technology 24(4):115 and Greene (1978) J. Vac. Sci. Technol. 15:1718.